This invention relates generally to semiconductor field-effect transistor (FET) circuits, and more particularly the invention relates to complementary FET logic circuits fabricated in compound semiconductor material.
Limitations of FET circuitry formed in compound semiconductor material such as gallium arsenide are speed and power dissipation. Interconnect lines at high fan-out increase the capacitive loading of complementary FET logic circuitry, thus increasing propagation time and reducing noise margin. FET circuits using only enhancement and depletion mode transistor pairs have increased power dissipation. In silicon logic circuits these problems have been minimized by merging bipolar and MOS devices, thereby achieving high current capabilities of the bipolar devices and the low power consumption of CMOS technology. Heretofore, however, compound semiconductor FET logic circuits have retained speed and power limitations.